Job Description

• • Physical Design
  • Job Location : Dallas, TX

• • • Perform all aspects of sign-off including power, timing, physical verification checks, and design closure.
    • Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.
    • Collaborate across teams (physical design, logic design, package, DFT and test).
    • Hands-on synthesis and PnR using industry standard tools for high-speed digital designs in advanced process nodes.

• • • Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.
    • 8 12++ years of experience in Physical Design and timing closure.
    • Hands-on experience in synthesis, PnR and STA using Cadence/Synopsys tools for complex digital designs in 7nm and below.
    • Must have experience of multiple large SoC tapeouts in advanced nodes including hands-on experience in chip-level physical design and STA closure.

• • Technology Node:

• • • TSMC and Samsung

• • • 7nm, 5nm, 3nm (or lower)

Disclaimer: E-Solutions Inc. provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, amnesty, or status as a covered veteran in accordance with applicable federal, state and local laws. We especially invite women, minorities, veterans, and individuals with disabilities to apply. EEO/AA/M/F/Vet/Disability."

Thanks and Regards,

Recruiter

Sundeep M

Desk-:+1 4085180027

Email:sundeep.m@e-solutionsinc.com

2N Market St, Suite # 400, San Jose, CA- 95113

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